1. Field of the Invention
The present invention relates to a counter circuit, and, more particularly relates to a counter circuit that can suitably count a clock signal in which hazard easily occurs. Furthermore, the present invention relates to a latency counter, and, more particularly relates to a latency counter that counts a latency of an internal command within a synchronous memory. Further, the present invention relates to a semiconductor memory device including such a latency counter and also relates to a data processing system including such a semiconductor memory device.
2. Description of Related Art
Synchronous memories represented by a synchronous DRAM (Synchronous Dynamic Random Access Memory) are widely used as a main memory or the like of personal computers. In the synchronous memory, data is inputted and outputted in synchronism with a clock signal supplied from a controller. Thus, when a higher-speed clock is used, the data transfer rate can be increased.
However, because a DRAM core is consistently operated by an analog operation also in the synchronous DRAM, a considerably weak charge needs to be amplified by a sensing operation. Accordingly, it is not possible to shorten the time from issuing a read command to outputting first data. After the elapse of a predetermined delay time from the read command is issued, the first data is outputted in synchronism with an external clock.
This delay time is generally called “CAS latency” and is set to an integral multiple of a clock cycle. For example, when the CAS latency is 5 (CL=5), the read command is fetched in synchronism with the external clock, and thereafter, the first data is outputted in synchronism with the external clock that is after five cycles. That is, the first data is outputted after the elapse of the five clocks. A counter that counts such latency is called “latency counter”.
As the latency counter, a circuit described in Japanese Patent Application Laid-open (JP-A) No. 2008-47267 proposed by the present inventor(s) is well known. The latency counter described in JP-A No. 2008-47267 includes a ripple counter that outputs a count value in a binary format and a point-shift FIFO circuit, in which by a count value of the ripple counter, an input gate and an output gate of the point-shift FIFO circuit are controlled. The reason for using the ripple counter as the counter circuit is due to a consideration of a point that hazard easily occurs in a clock signal that should be counted.
That is, in the general DRAM, a DLL (Delay Locked Loop) circuit is used, and data is inputted and outputted in synchronism with an output clock generated by the DLL circuit. The DLL circuit always operates in a normal mode; however, when it is entered in a power-down mode or the like, its operation is stopped due to reduction of power consumption. Thus, upon returning from the power-down mode to the normal mode, a state that the output clock is temporarily unstable occurs, and hazard is sometimes outputted.
When hazard occurs in the output clock, if a ring counter in which shift registers are circulation-connected is used, for example, the count value sometimes fluctuates. That is, in the ring counter, it is necessary that the number of registers to which an active level is latched is one. However, there is sometimes a state that the active level is latched to two or more registers by hazard, or the active level is not latched to any register. When the ring counter is in such a state, the count value fluctuates and the operation of the latency counter is disabled.
Such problems can be solved by using a ripple counter in which a counting operation is performed in a binary format. That is, the ripple counter is deemed not to experience a state that the count value fluctuates, and thus, even when the count value is made to jump wrongly by hazard, the count value can be used as is. Due to these reasons, in the latency counter in JP-A No. 2008-47267, the ripple counter is used as the counter circuit.
Japanese Patent Application Laid-open No. 2007-115351 discloses a similar circuit, as another patent document related to the latency counter.
As described above, as a countermeasure against hazard, it is very effective to use the ripple counter as the counter circuit used for the latency counter. However, in the ripple counter, a count value changes more belatedly in higher-order bits. Thus, when the frequency of the clock signal is very high, there can be a case that the output of the count value is not in time for the operation of the FIFO circuit, depending upon a certain situation.
Such a problem occurs not only in the counter circuit for a latency counter but also in overall counter circuits that need to count a high-frequency signal in which hazard or the like is easily generated.